critical path delay的意思|示意
关键路径延迟
critical path delay的网络常见释义
径延迟 ...能: 在电路上我们虽然增加额外的过滤器电 路,但是并不会影响到整体处理器的效能,因 为经过验证最长路径延迟(Critical Path Delay)仍 然小于指令快取记忆体(I-Cache Memory)的存 取时间,不会造成时脉周期延长的后遗症,所 以可以保持处理器效能。
critical path delay相关例句
The ‘Task Resource Float’ is the amount of delay that can be applied to a task, performed by a Resource, without introducing a delay into another Critical Path task, performed by the same Resource.
任务资源浮动是指用到同一资源时，在不会另一个关键路径任务延迟的情况下，一个任务可以被延迟的时间。
The multiplier in this paper is Bit-serial mode and the new hardware architecture is regular which reduces the delay of the critical path.
新的乘法器采用比特串行方式，使得硬件结构更加规则，减少了原有乘法器关键路径的延迟。
Through the synthesis of MAC circuit, it validates that the ideas and methods presented in the paper do well to reduce the critical path delay and circuit gates.
电路综合实验表明采用本文所提出思想和方法可以有效减少MAC关键路径时延和电路门数。
Because of the decreased critical path delay, the conversion can be implemented in a single cycle.
关键路径延时的减小，使这一转换可以在单周期内完成。
It's critical path delay is very little, and it operates in the fully-pipelined continuous decoding manner.
它关键路径延时很小，并且为全流水线连续解码工作方式。
The improved lifting scheme is adopted to reduce the critical path delay.
采用改进的提升算法，减少了关键路径上的延时。