lock-loop的意思|示意

In frequency synthesis by phase lock, the loop gain will vary by the same amount due to this effect, which generally im - pedes optimization of loop performance.

在锁相频率合成器中，由于压控灵敏度的变化，环路增益也将产生同样大小的变化，这就妨碍了环路特性的最佳化。

We begin our discussion with a description of an imbalance OQPSK model, then analyze the effect on carrier tracking loop steady-state lock point and the effect on average BEP.

通过对OQPS K调制器不均衡的模型讨论，深刻分析了调制器不均衡对载波跟踪环路稳态锁定点和平均BEP的影响。

The Digital Phase Lock Loop(DPLL)is the core of the coherent demodulation.

数字锁相环路（DPLL）是数字相干解调技术的核心。

Digital phase lock loop base on fuzzy logical control, which is used to recover carrier in communication system.

基于模糊逻辑控制的数字锁相环，用于通信系统中的载波恢复。

We begin our discussion with a description of an imbalance model, then analyse its effect on carrier tracking loop steady-state lock point and its effect on average BEP.

通过对调制器不均衡的模型讨论，深刻分析了调制器不均衡对载波跟踪环路稳态锁定点和平均BEP的影响。

Because of the frequency lock loop traction PLL filter can be designed very narrow, with very good noise suppression performance, to meet the precise requirements of carrier phase tracking.

由于有锁频环的频率牵引，锁相环路滤波器可以设计得很窄，具有很好的抑噪性能，满足精确跟踪载波相位的要求。