sample-hold circuit的意思|示意

The sample and hold circuit is employed by the bottom plate sampling technique, which could not only cancel the charge injection error but also eliminate the effect of clock feed-through.

采样保持电路设计采用了电容下极板采样技术，不仅有效地避免了电荷注入效应引起的采样信号失真，而且消除了时钟馈通效应的不良影响。

Sample the negative voltage on the diode series with IGBT by Peak hold switch circuit, and cut-in A/D module in the DSP, compared with setting value.

通过电压峰值采样保持电路对IGBT串联二极管反压值进行采样，后经DSP A/D转换模块与反压设定值进行比较。

On the basis of analyzing the common methods of background magnetic field compensation, a new automatic compensation method based on sample and hold circuit is put forward.

在分析磁通门常用背景磁场补偿方法基础上，提出一种新的采样保持电路自动补偿方法。

Sample and Hold, Voltage Reference Circuit design.

采样保持电路、电压源电路设计。

Sampling rate and holding accuracy are two most concerned targets in designing the sample-and-hold circuit.

采样速度和保持精度，是采样保持电路设计制作者最为关注的两项指标。

The key circuit design includes a sample-and-hold gain circuit using switched-capacitor to sample or hold the signal and a preamplifier-latch comparator using two-phase clock.

在电路设计中主要包括开关电容采样的全差分运放组成的采保增益电路和两相时钟控制的带预放大器的锁存比较器。