Delay-Locked Loop的意思|示意
延迟锁相环延迟锁定环路
Delay-Locked Loop的网络常见释义
延迟锁相环 ...科技_论文宝库 中文关键词： DDR3 SDRAM,物理层,延迟锁相环,压控延迟线,鉴相器 中文摘要： 延迟锁相环(Delay-Locked Loop,DLL)因具备时钟定位准确、抗抖动能力强、锁定速度快等优点,在各种时序系统中得到了广泛应用。
锁相环 高精度高速A/D转换器时钟稳定电路设计 钟信号相位,以使输入时钟的占空比接近50%,抖动小于0.5ps。 ◇ 延迟锁相环（dll） 延迟锁相环（delay-locked loop,dll）的结构与普通锁相环（phase-locked loop,pll）相似,它只是用电压控制延迟线（vcd
Delay-Locked Loop相关短语
1、 Delay Locked Loop 延迟锁相环 ; 延迟锁定环 ; 延迟锁定环路 ; 环路有延迟锁相环
2、 DLL Delay-Locked Loop 延时锁定循环电路
3、 delay locked loop dll 延迟锁定环路
Delay-Locked Loop相关例句
In this paper we introduce the developmental phase and experimental equipments of long time delay phase-locked loop and also give the field test results via the satellite "Symphonic".
本文叙述了长延时锁相环的研制情况和实验设备，同时也给出了通过“交响乐”卫星的现场试验结果。
To this end the current multipath estimation delay locked loop(MEDLL) was investigated and improvements were proposed based on the zero-point fixed principle.
为了消除扩频系统中的多径干扰，文章基于稳态零点不变的原则对多径估计延迟锁相环（MEDLL）进行研究及改进。
In this paper, a low-jitter process-independent DLL(delay locked loop) based on self-biased techniques is presented.
本文给出了一种采用自偏置技术的低抖动延迟锁相环，可应用于高频时钟产生电路。
During the design of delay - locked loop, the frame of the whole circuit is introduced and then the principles and implementation of the basic modules are presented.
在数字延迟锁相环设计中，先整体讲述电路的整体构架的设计，然后详细阐述了基本模块的实现方法与原理。
Theoretical and numerical results show that the new scheme has an improved performance and remarkable complexity simplicity as compared with the classical digital delay-locked loop.
理论分析和数值结果表明，该方案较传统的延迟锁定跟踪方案明显降低了实现复杂度，而且性能有所提高。
Unlike previous researches, the nonlinear analysis on the effects of delay-difference module employed in the delay phase-locked loop (DPLL)is particularly presented.
与以往研究不同，针对延迟锁相线性化环路的延迟差分环节，着重分析了其非线性特性对环路性能的影响。